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_______________general description the max509/max510 are quad, serial-input, 8-bit volt- age-output digital-to-analog converters (dacs). they operate with a single +5v supply or dual ?v supplies. internal, precision buffers swing rail-to-rail. the refer- ence input range includes both supply rails. the max509 has four separate reference inputs, allow- ing each dac's full-scale range to be set independently. 20-pin dip, ssop, and so packages are available. the max510 is identical to the max509 except it has two ref- erence inputs, each shared by two dacs. the max510 is housed in space-saving 16-pin dip and so packages. the serial interface is double-buffered: a 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit dac registers. a 12-bit serial word is used to load data into each register. both input and dac regis- ters can be updated independently or simultaneously with single software commands. two additional asyn- chronous control pins provide simultaneous updating ( ldac ) or clearing ( clr) of input and dac registers. the interface is compatible with microwire tm and spi/ qspi tm . all digital inputs and outputs are ttl/cmos compatible. a buffered data output provides for read- back or daisy-chaining of serial devices. ____________________________features ? single +5v or dual ?v supply operation ? output buffer amplifiers swing rail-to-rail ? reference input range includes both supply rails ? calibrated offset, gain, and linearity (1lsb tue) ? 10mhz serial interface, compatible with spi, qspi (cpol = cpha = 0) and microwire ? double-buffered registers for synchronous updating ? serial data output for daisy-chaining ? power-on reset clears serial interface and sets all registers to zero ______________ordering information ordering information continued on last page. * dice are specified at +25?, dc parameters only. **contact factory for availability and processing to mil-std-883. max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 outc outd v dd refc refb v ss outa outb top view max509 refd cs n.c. sclk dgnd n.c. agnd refa din clr dout ldac dip/so/ssop _________________pin configurations max509 outa dac a dac b dac c dac d refa refb dac reg a decode control input reg a dac reg b input reg b dac reg c input reg c dac reg d input reg d 12-bit shift register sr control cs din sclk refc refd outb outc outd dout ldac clr v dd dgnd v ss agnd _______________functional diagrams 19-0155; rev 2; 1/96 part temp. range pin-package max509 acpp 0? to +70? 20 plastic dip max509bcpp 0? to +70? 20 plastic dip max509acwp 0? to +70? 20 wide so ? ? 1/2 ? max509bcwp 20 wide so ? 1/2 max509acap 0? to +70? 20 ssop ? 0? to +70? max509bcap 0? to +70? 20 ssop ? 1/2 max509bc/d 0? to +70? dice* ? 1/2 pin configurations continued at end of data sheet. functional diagrams continued at end of data sheet. tue (lsb) microwire is a trademark of national semiconductor. spi and qspi are trademarks of motorola. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs 2 _______________________________________________________________________________________ v dd to dgnd ..............................................................-0.3v, +6v v dd to agnd...............................................................-0.3v, +6v v ss to dgnd ...............................................................-6v, +0.3v v ss to agnd ...............................................................-6v, +0.3v v dd to v ss .................................................................-0.3v, +12v digital input voltage to dgnd ......................-0.3v, (v dd + 0.3v) ref_....................................................(v ss - 0.3v), (v dd + 0.3v) out_..............................................................................v dd , v ss maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 16-pin plastic dip (derate 10.53mw/? above +70?) ....842mw 16-pin wide so (derate 9.52mw/? above +70?) .........762mw 16-pin cerdip (derate 10.00mw/? above +70?) ........800mw 20-pin plastic dip (derate 11.11mw/? above +70?)....889mw 20-pin wide so (derate 10.00mw/? above +70?) .......800mw 20-pin ssop (derate 10.00mw/? above +70?) ............800mw 20-pin cerdip (derate 11.11mw/? above +70?) ........889mw operating temperature ranges: max5_ _ _c_ _ .....................................................0? to +70? max5_ _ _e_ _ ..................................................-40? to +85? max5_ _ _mj_ ................................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+300? electrical characteristics (v dd = +5v ?0%, v ss = 0v to -5.5v, v ref = 4v, agnd = dgnd = 0v, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter conditions min typ max units note: the outputs may be shorted to v dd , v ss , or agnd if the package power dissipation is not exceeded. typical short-circuit current to agnd is 50ma. do not bias agnd more than +1v above dgnd, or more than 2.5v below dgnd. absolute maximum ratings resolution 8 bits ? max5_ _a vref = +4v, v ss = 0v or -5v ?0% max5_ _b ? max5_ _a total unadjusted error vref = -4v, v ss = -5v ?0% ?.5 lsb differential nonlinearity ? lsb guaranteed monotonic 14 max5_ _c 16 max5_ _e max5_ _b ?0 ?/? code = ff hex 14 max5_ _c full-scale error ?4 mv code = ff hex ?0 ?/? code = 00 hex zero-code-error supply rejection 12 mv code = 00 hex, v ss = 0v 20 max5_ _m symbol tue dnl ?4 max5_ _c ?6 max5_ _e zero-code error code = 00 hex, v ss = -5v ?0% ?0 mv max5_ _m zce ?.5 code = 00 hex, v dd = 5v ?0%, v ss = 0v or -5v ?0% zero-code temperature coefficient 18 max5_ _e full-scale-error supply rejection code = ff hex, v dd = +5v ?0%, v ss = 0v or -5v ?0% 112 mv max5_ _m full-scale-error temperature coefficient static accuracy
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v ?0%, v ss = 0v to -5.5v, v ref = 4v, agnd = dgnd = 0v, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.) parameter conditions min typ max units input voltage range symbol v ss v dd v max509 16 24 max510 input resistance (note 1) 812 k code = 55 hex max509 15 (note 4) ac feedthrough -70 db (note 3) channel-to-channel isolation -60 db max510 input capacitance (note 2) 30 pf code = 00 hex 10 2 vref = 4v, load regulation 1/4lsb 2 full-scale output voltage v ss v dd v resistive load 10 k input high voltage 2.4 v v ih vref = -4v, v ss = -5v ?0%, load regulation 1/4lsb vref = v dd max5_ _c/e, load regulation 1lsb vref = v dd max5_ _m, load regulation 2lsb input low voltage 0.8 v v il v in = 0v or v dd input current 1.0 ? i in (note 5) input capacitance 10 pf c in i source = 0.2ma output high voltage v dd - 0.5 v v oh i sink = 1.6ma output low voltage 0.4 v v ol max5_ _e 0.7 max5_ _c 1.0 max5_ _m voltage-output slew rate 0.5 v/? positive and negative to 1/2lsb, 10k ii 100pf load output settling time (note 6) 6 ? digital feedthrough 5 nv-s wideband amplifier noise 60 mhz vref = 0.5v p-p , 3db bandwidth multiplying bandwidth 1 vref = 4v p-p at 1khz, v dd = 5v, code = ff hex digital-to-analog glitch impulse 87 code 128 y 127 12 nv-s code = 00 hex, all digital inputs from 0v to v dd signal-to-noise + distortion ratio vref = 4v p-p at 20khz, v ss = -5v ?0% 74 db sinad ? rms reference inputs dac outputs digital inputs digital outputs dynamic performance
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +5v ?0%, v ss = 0v to -5.5v, v ref = 4v, agnd = dgnd = 0v, r l = 10k , c l = 100pf, t a = t min to t max , unless otherwise noted.) parameter conditions min typ max units positive supply voltage symbol 4.5 5.5 v for specified performance v dd negative supply voltage -5.5 0 v for specified performance v ss 510 positive supply current 512 ma i dd negative supply current ma i ss 510 max5_ _c/e max5_ _m max5_ _c/e 512 max5_ _m v ss = -5v ?0%, outputs unloaded, all digital inputs = 0v or v dd note 1: input resistance is code dependent. the lowest input resistance occurs at code = 55 hex. note 2: input capacitance is code dependent. the highest input capacitance occurs at code = 00 hex. note 3: vref = 4v p-p , 10khz. channel-to-channel isolation is measured by setting the code of one dac to ff hex and setting the code of all other dacs to 00 hex. note 4: vref = 4v p-p , 10khz. dac code = 00 hex. note 5: guaranteed by design. note 6: output settling time is measured by taking the code from 00 hex to ff hex, and from ff hex to 00 hex. timing characteristics (v dd = +5v ?0%, v ss = 0v to -5v, v ref = 4v, agnd = dgnd = 0v, c l = 50pf, t a = t min to t max , unless otherwise noted.) parameter conditions min typ max units clr pulse width low symbol 50 25 ns max5_ _m max5_ _c/e 40 20 t clw max5_ _m 50 25 ns max5_ _c/e 40 20 sclk fall to cs rise hold time 0 ns t csh2 sclk fall to cs fall hold time 0 ns (note 7) t csh0 40 max5_ _c/e 10 100 max5_ _c/e max5_ _c/e 40 40 max5_ _c/e 20 12.5 max5_ _c/e din to sclk rise hold time 0 ns t dh sclk rise to cs rise hold time (note 9) 40 ns t csh1 ldac pulse width low (notes 7, 8) 0 ns t ldw t cll cs rise to ldac fall setup time 40 max5_ _c/e cs fall to sclk setup time 50 ns max5_ _m t css din to sclk rise setup time 50 ns max5_ _m t ds sclk clock frequency 20 10 mhz max5_ _m f clk sclk pulse width high 50 ns max5_ _m t ch sclk pulse width low max5_ _m 50 ns t cl sclk to dout valid 10 100 ns max5_ _m t do note 7: guaranteed by design. note 8: if ldac is activated prior to cs 's rising edge, it must stay low for t ldw or longer after cs goes high. note 9: minimum delay from 12th clock cycle to cs rise. outputs unloaded, all digital inputs = 0v or v dd power supplies serial interface timing
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 5 12 0 0 1.2 output sink current vs. (v out - v ss ) 2 10 max509-fg01 v out - v ss (v) i out (ma) 0.8 6 4 0.2 0.6 1.0 8 0.4 v dd = vref = +5v v ss = gnd = 0v all digital inputs = 00 hex -25 0 3.6 4.6 -20 max509-fg10 v out (v) i out (ma) 4.4 -10 -5 3.8 4.0 -15 output source current vs. output voltage 4.8 5.0 4.2 v dd = vref = +5v v ss = gnd digital input = ff hex 7 0 -60 -20 40 100 supply current vs. temperature 2 6 max509-fg02 temperature ( c) supply current (ma) 20 80 4 5 3 1 -40 0 60 120 140 i dd i ss v dd = +5.5v v ss = -5.5v vref = -4.75 all digital inputs = +5v 6 0 -5 5 supply current vs. reference voltage 1 5 max509-fg03 vref voltage (v) i dd (ma) 0 3 2 -4 -2 2 4 4 3 1 -1 -3 v dd = +5v all logic inputs = +5v v ss = -5v v ss = 0v 0 1k 10k 100k reference voltage input frequency response -40 max509-fg06 frequency (hz) relative output (db) -30 -20 -10 1m 10m v dd = +5v v ss = agnd vref = 2.5vdc + 0.5vp-p sine wave -40 -90 02 6 10 thd + noise at dac output vs. reference amplitude -80 -50 max509-fg04 reference amplitude (vp-p) thd + noise (db) 48 -60 -70 -85 -75 -65 -55 -45 1% 0.01% 0.1% freq = 20khz freq = 1khz v dd = +5v v ss = -5v input code = ff hex thd + noise (%) -20 -80 10 1k 100k thd + noise at dac output vs. reference frequency -70 max509-fg05 reference frequency (hz) thd + noise (db) -60 -50 -40 -90 -30 100 10k vref = 8vp-p vref = 1vp-p vref = 4vp-p v dd = +5v v ss = -5v input code = ff hex freq = swept 10% 1% 0.1% 0.01% thd + noise (%) 0 1k 10k 100k reference voltage input frequency response -40 max509-fg07 frequency (hz) relative output (db) -30 -20 -10 1m 10m v dd = +5v v ss = agnd vref = 2.5vdc + 0.05vp-p sine wave 0 1k 10k 100k reference voltage input frequency response -40 max509-fg08 frequency (hz) relative output (db) -30 -20 -10 1m 10m v dd = +5v v ss = -5v vref = 2.5vdc + 4vp-p sine wave __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.)
max509/max510 quad, serial 8-dacs with rail-to-rail outputs 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) a = refa, 10v p-p b = outa, 100 m v/div, unloaded timebase = 10 m s/div v dd = +5v, v ss = -5v code = all 0s reference feedthrough at 40khz a b a = refa, 10v p-p b = outa, 50 m v/div, unloaded timebase = 1ms/div reference feedthrough at 400hz a b a = refa, 10v p-p b = outa, 50 m v/div, unloaded timebase = 50 m s/div reference feedthrough at 10khz a b 5v 50? 100? a = refa, 10v p-p b = outa, 50 m v/div, unloaded timebase = 100 m s/div reference feedthrough at 4khz a b 10 5.0 3.6 0-4 zero-code error vs. negative supply voltage 3.8 4.8 max509-fg09 v ss (v) zero-code error (mv) -3 4.4 4.0 -1 -2 4.6 3.4 4.2 -5 -6 v dd = +5v vref = +4v a = cs, 2v/div b = outa, 20mv timebase = 200ns/div worst-case 1lsb digital step change a b 200ns 2v 20mv
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 7 5v 100mv 1? a = digital input, 5v/div b = out_ , 2v/div timebase = 1 m s/div v dd = +5v ref_ = +4v all bits off to all bits on r l = 10k w , c l = 100pf positive settling time (v ss = agnd or -5v) a b 5v 100mv 1? a = digital input, 5v/div b = out_ , 2v/div timebase = 1 m s/div v dd = +5v ref_ = +4v all bits on to all bits off r l = 10k w , c l = 100pf negative settling time (v ss = agnd) a b ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) a = sclk, 333khz b = out_, 10mv/div timebase = 2 m s/div clock feedthrough a b 5v 100mv 1? a = digital input, 5v/div b = out_ , 2v/div timebase = 1 m s/div v dd = +5v ref_ = +4v all bits on to all bits off r l = 10k w , c l = 100pf negative settling time (v ss = -5v) a b
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs 8 _______________________________________________________________________________________ name function 1 outb dac b voltage output 2 outa dac a voltage output 3 v ss negative power supply, 0v to -5v ?0%. connect to agnd for single-supply operation. pin max509 max510 1 2 4 refb reference voltage input for dac b refab reference voltage input for dacs a and b 5 refa reference voltage input for dac a 6 agnd analog ground 3 4 7, 14 n.c. not internally connected 8 dgnd digital ground 5 6 ______________________________________________________________pin description 10 dout 8 9 ldac 7 11 clr 9 12 din 10 13 sclk 11 15 cs 12 16 refd reference voltage input for dac d refcd reference voltage input for dacs c and d 13 load dac input (active low). driving this asynchronous input low (level sensitive) transfers the contents of each input latch to its respective dac latch. serial data output. can sink and source current. data at dout is adjustable to be clocked out on rising or falling edge of sclk. 17 refc reference voltage input for dac c 18 v dd positive power supply, +5v ?0% 14 19 outd dac d output voltage 15 20 outc dac c output voltage 16 clear dac input (active low). driving clr low causes an asynchronous clear of input and dac registers and sets all dac outputs to zero. serial data input. ttl/cmos-compatible input. data is clocked into din on the rising edge of sclk. cs must be low for data to be clocked in. serial clock input. data is clocked in on the rising edge and clocked out on either the rising (default) or the falling edge. chip-select input (active low). data is shifted in and out when cs is low. programming commands are executed when cs rises.
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs _______________________________________________________________________________________ 9 a1 a0 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb daca data from previous data input data from previous data input a1 a0 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb dacd a1 a1 a1 a1 a0 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 a1 a0 c1 c0 d7 a0 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 a1 a1 a0 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 a1 d6 d5 d4 d3 d2 d1 d0 a1 a1 dout mode 0 dout mode 1 (default) din sclk cs instruction executed figure 1. max509/max510 3-wire interface timing _______________detailed description serial interface at power-on, the serial interface and all dacs are cleared and set to code zero. the serial data output (dout) is set to transition on sclk's rising edge. the max509/max510 communicate with microproces- sors through a synchronous, full-duplex, 3-wire inter- face (figure 1). data is sent msb first and can be transmitted in one 4-bit and one 8-bit (byte) packet or in one 12-bit word. if a 16-bit control word is used, the first four bits are ignored. a 4-wire interface adds a line for ldac and allows asynchronous updating. the serial clock (sclk) synchronizes the data transfer. data is transmitted and received simultaneously. figure 2 shows a detailed serial interface timing. please note that the clock should be low if it is stopped between updates. dout does not go into a high- impedance state if the clock or cs is high. serial data is clocked into the data registers in msb- first format, with the address and configuration infor- mation preceding the actual dac data. data is clocked in on sclk's rising edge while cs is low. data at dout is clocked out 12 clock cycles later, either at sclk's rising edge (default or mode 1) or falling edge (mode 0). chip select ( cs ) must be low to enable the dac. if cs is high, the interface is disabled and dout remains unchanged. cs must go low at least 40ns before the first rising edge of the clock pulse to properly clock in the first bit. with cs low, data is clocked into the max509/max510's internal shift register on the rising edge of the external serial clock. sclk can be driven at rates up to 12.5mhz.
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs 10 ______________________________________________________________________________________ t ldw sclk din dout ldac cs t do t dh t ds t csh0 t css t ch t cl t csh1 t csh2 t cll note: timing specification t cll is recommended to minimize output glitch, but is not mandatory. figure 2. detailed serial interface timing (mode 0 shown) table 1. serial-interface programming commands mode 0, dout clocked out on falling edge of sclk. all dacs updated from input registers. mode 1, dout clocked out on rising edge of sclk (default). all dacs updated from respective input registers. ldac ?command, all dacs updated from respective input registers. 12-bit serial word 0 0 1 1 0 0 1 1 c0 0 0 0 0 0 1 1 1 1 1 1 1 1 c1 1 1 1 0 0 1 1 1 1 0 0 0 0 a0 0 1 x 1 0 0 1 0 1 0 1 0 1 function ldac d7 . . . . . . . . d0 a1 x x x x x x x x x 1 x x x x x x x x x 1 x x x x x x x x x 0 no operation (nop), shifts data in shift register. x x x x x x x x x x update all dacs from shift register. x 8-bit dac data x load input and dac register a. load input and dac register b. load input and dac register c. load input and dac register d. 1 1 1 1 8-bit dac data 8-bit dac data 8-bit dac data 8-bit dac data load dac a input register, dac output unchanged. load dac b input register, dac output unchanged. load dac c input register, dac output unchanged. load dac d input register, dac output unchanged. 1 1 1 1 8-bit dac data 8-bit dac data 8-bit dac data 8-bit dac data
serial input data format and control codes the 12-bit serial input format shown in figure 3 com- prises two dac address bits (a1, a0), two control bits (c1, c0) and eight bits of data (d0...d7). the 4-bit address/control code configures the dac as shown in table 1. load input register, dac registers unchanged (single update operation) when performing a single update operation, a1 and a0 select the respective input register. at the rising edge of cs , the selected input register is loaded with the cur- rent shift-register data. all dac outputs remain unchanged. this preloads individual data in the input register without changing the dac outputs. load input and dac registers this command directly loads the selected dac register at cs 's rising edge. a1 and a0 set the dac address. current shift-register data is placed in the selected input and dac registers. for example, to load all four dac registers simultaneously with individual settings (dac a = 1v, dac b = 2v, dac c = 3v and dac d = 4v), five commands are required. first, perform four single input register update opera- tions. next, perform an ldac ?command as a fifth command. all dacs will be updated from their respec- tive input registers at the rising edge of cs . update all dacs from shift registers all four dac registers are updated with shift-register data. this command allows all dacs to be set to any analog value within the reference range. this command can be used to substitute clr if code 00 hex is pro- grammed, which clears all dacs. no operation (nop) the nop command (no operation) allows data to be shift- ed through the max509/max510 shift register without affecting the input or dac registers. this is useful in daisy chaining (also see the daisy-chaining devices section). for this command, the data bits are "don't cares." as an example, three max509/max510s are daisy-chained (a, b and c), and dac a and dac c need to be updated. the 36-bit-wide command would consist of one 12-bit word for device c, followed by an nop instruction for device b and a third 12-bit word with data for device a. at cs 's rising edge, only device b is not updated. ?dac?command (software) all dac registers are updated with the contents of their respective input registers at cs 's rising edge. with the exception of using cs to execute, this performs the same function as the asynchronous ldac . set dout phase ?sclk rising (mode 1, default) mode 1 resets the serial output dout to transition at sclk's rising edge. this is the max509/max510? default setting after the supply voltage has been applied. the command also loads all dac registers with the con- tents of their respective input registers, and is identical to the ldac command. max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 11 this is the first bit shifted in a1 a0 c1 c0 d7 d6 l l l d1 d0 din dout control and address bits 8-bit dac data msb lsb figure 3. serial input format ( ldac = h) ( ldac = x) ( ldac = x) ( ldac = x) ( ldac = x) ( ldac = h) 1 0 1 1 xxxxxxxx d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 a0 a1 8-bit dac data 0 0 x 0 d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 a0 a1 xxx xx xxx 0 0 x 1 d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 a0 a1 1 0 0 x xx x xx x xx d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 a0 a1 8-bit data 0 1 address d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 a0 a1 8-bit data 1 1 address d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 a0 a1
set dout phase ?sclk falling (mode 0) this command resets dout to transition at sclk's falling edge. once this command is issued, the phase of dout is latched and will not change except on power-up or if the specific command is issued that sets the phase to rising edge. the same command also updates all dac registers with the contents of their respective input registers, identical to the ldac ?command. ldac operation (hardware) ldac is typically used in 4-wire interfaces (figure 7). ldac allows asynchronous hardware control of the dac outputs and is level-sensitive. with ldac low, the dac reg- isters are transparent and any time an input register is updated, the dac output immediately follows. clear dacs with clr strobing the clr pin low causes an asynchronous clear of input and dac registers and sets all dac outputs to zero. similar to the ldac pin, clr can be invoked at any time, typically when the device is not selected ( cs = h). when the dac data is all zeros, this function is equivalent to the "update all dacs from shift registers" command. digital inputs and outputs digital inputs and outputs are compatible with both ttl and 5v cmos logic. the power-supply current (i dd ) depends on the input logic levels. using cmos logic to drive cs , sclk, din, clr and ldac turns off the internal level trans- lators and minimizes supply currents. serial data output dout is the output of the internal shift register. dout can be programmed to clock out data on sclk's falling edge (mode 0) or rising edge (mode 1). in mode 0, output data lags the input data by 12.5 clock cycles, maintaining compatibility with microwire, spi, and qspi. in mode 1, output data lags the input by 12 clock cycles. on power-up, dout defaults to mode 1 timing. dout never three-states; it always actively drives either high or low and remains unchanged when cs is high. interfacing to the microprocessor the max509/max510 are microwire, spi, and qspi compati- ble. for spi and qspi, clear the cpol and cpha configura- tion bits (cpol = cpha = 0). the spi/qspi cpol = cpha = 1 configuration can also be used if the dout output is ignored. the max509/max510 can interface with intel's 80c5x/80c3x family in mode 0 if the sclk clock polarity is inverted. more universally, if a serial port is not available, three lines from one of the parallel ports can be used for bit manipulation. digital feedthrough at the voltage outputs is greatly mini- mized by operating the serial clock only to update the regis- ters. also see the clock feedthrough photo in the typical operating characteristics section. the clock idle state is low. daisy-chaining devices any number of max509/max510s can be daisy-chained by connecting the dout pin of one device to the din pin of the following device in the chain. the nop instruction (table 1) allows data to be passed from din to dout without chang- ing the input or dac registers of the passing device. a three- wire interface updates daisy-chained or individual max509/max510s simultaneously by bring ing cs high. quad, serial 8-bit dacs with rail-to-rail outputs 12 ______________________________________________________________________________________ sclk din dout cs sk so si i/0 microwire port max509 max510 the dout-si connection is not required for writing to the max509/max510, but may be used for read-back purposes. figure 4. connections for microwire dout din sclk cs miso mosi sck i/0 spi port max509 max510 the dout-miso connection is not required for writing to the max509/max510, but may be used for read-back purposes. cpol = 0, cpha = 0 figure 5. connections for spi ( ldac = x) a1 a0 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx 1 0 1 0 max509/max510
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 13 sclk din cs max509 max510 sclk din cs max509 max510 sclk din cs max509 max510 sclk din cs max509 max510 dout dout dout sclk din cs sclk din cs to other serial devices figure 6. daisy-chained or individual max509/max510s are simultaneously updated by bringing cs high. only three wires are required. cs ldac sclk din max509 max510 cs ldac sclk din max509 max510 cs ldac sclk din max509 max510 to other serial devices din sclk ldac cs1 cs2 cs3 figure 7. multiple max509/max510 dacs sharing one din line. simultaneously update by strobing ldac, or specifically update by enabling individual cs.
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs 14 ______________________________________________________________________________________ if multiple devices share a common din line, figure 7's configuration provides simultaneous update by strob- ing ldac low. cs1 , cs2 , cs3 ... are driven separately, thus controlling which data are written to devices 1, 2, 3.... analog section dac operation the max509/max510 contain four matched voltage- output dacs. the dacs are inverted r-2r ladder net- works that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied ref- erence voltages. each dac in the max509 has a sepa- rate reference input, while the two reference inputs in the max510 each share a pair of dacs. the two refer- ence inputs permit different full-scale output voltage ranges for each pair of dacs. a simplified diagram of one of the four dacs is shown in figure 8. reference input the max509/max510 can be used for multiplying applications. the reference accepts both dc and ac signals. the voltage at each ref input sets the full- scale output voltage for its respective dac(s). if the ref- erence voltage is positive, both the max509 and max510 can be operated from a single supply. if dual supplies are used, the reference input can vary from v ss to v dd , but is always referred to agnd. the input impedance at ref is code dependent, with the lowest value (16k for the max509 and 8k for the max510) occurring when the input code is 55 hex or 0101 0101. the maximum value, practically infinity, occurs when the input code is 00 hex. since the ref input imped- ance is code dependent, the dac's reference sources must have a low output impedance (no more than 32 for the max509 and 16 for the max510) to maintain output linearity. the ref input capacitance is also code dependent: 15pf typical for the max509 and 30pf typical for the max510. the output voltage for any dac can be represented by a digitally programmable voltage source as: vout = (nb x vref) / 256 where nb is the numerical value of the dac's binary input code. output buffer amplifiers all max509/max510 voltage outputs are internally buffered by precision unity-gain followers that slew at up to 1v/?. the outputs can swing from v ss to v dd . with a 0v to +4v (or +4v to 0v) output transition, the amplifier outputs will settle to 1/2lsb in typically 6s when loaded with 10k in parallel with 100pf. the buffer amplifiers are stable with any combination of resistive loads 3 2k and capacitive loads 300pf. __________applications information power supply and reference operating ranges the max509/max510 are fully specified to operate with v dd = 5v ?0% and v ss = 0v to -5.5v. 8-bit perfor- mance is guaranteed for both single- and dual-supply operation. the zero-code output error is less than 14mv when operating from a single +5v supply. the dacs work well with reference voltages from v ss to v dd . the reference voltage is referred to agnd. the preferred power-up sequence is to apply v ss and then v dd , but bringing up both supplies at the same time is also acceptable. in either case, the voltage applied to ref should not exceed v dd during power- up or at any other time. if proper power sequencing is not possible, connect an external schottky diode between v ss and agnd to ensure compliance with the absolute maximum ratings . do not apply signals to the digital inputs before the device is fully powered up. power-supply bypassing and ground management in single-supply operation (agnd = dgnd = v ss = 0v), agnd, dgnd and v ss should be connected together in a "star" ground at the chip. this ground should then return to the highest quality ground avail- able. bypass v dd with a 0.1? capacitor, located as close to v dd and dgnd as possible. in dual-supply operation, bypass v ss to agnd with 0.1?. careful pc board layout minimizes crosstalk among dac outputs, reference inputs, and digital inputs. figures 9 and 10 show suggested circuit board layouts to minimize crosstalk. 2r r rr 2r 2r 2r 2r 2r d0 d5 d6 d7 ref_ agnd shown for all 1 on dac out_ figure 8. dac simplified circuit diagram
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 15 unipolar-output, 2-quadrant multiplication in unipolar operation, the output voltages and the refer- ence input(s) are the same polarity. figures 11 and 12 show the max509/max510 unipolar configurations. both devices can be operated from a single supply if the reference inputs are positive. if dual supplies are used, the reference input can vary from v ss to v dd . table 2 shows the unipolar code. bipolar-output, 2-quadrant multiplication bipolar-output, 2-quadrant multiplication is achieved by offsetting agnd positively or negatively. table 3 shows the bipolar code. agnd can be biased above dgnd to provide an arbi- trary nonzero output voltage for a 0 input code, as shown in figure 13. the output voltage at outa is: v outa = v bias + (nb/256)(v in ), figure 9. suggested max509 pc board layout for minimizing crosstalk (bottom view) outc outd v dd refc refd outb outa v ss refb refa system gnd agnd figure 10. suggested max510 pc board layout for minimizing crosstalk (bottom view) outc outd v dd refcd outb outa v ss refab system gnd agnd dac contents msb lsb analog output 1 1 1 1 1 1 1 1 255 +v ref ( ) 256 1 0 0 0 0 0 0 1 129 +v ref ( ) 256 1 0 0 0 0 0 0 0 128 v ref +v ref ( ) = + 256 2 0 1 1 1 1 1 1 1 127 +v ref ( ) 256 0 0 0 0 0 0 0 0 0v 0 0 0 0 0 0 0 1 1 +v ref ( ) 256 table 2. unipolar code table 1 note: 1lsb = (v ref ) (2 -8 ) = +v ref ( ) 256 table 3. bipolar code table 1 0 0 0 dac contents 0 0 0 1 msb lsb analog output 1 1 1 1 1 1 1 1 127 +v ref ( ) 128 1 +v ref ( ) 128 1 0 0 0 0 0 0 0 0v 0 1 1 1 1 1 1 1 1 -v ref ( ) 128 0 0 0 0 0 0 0 0 128 -v ref ( ) = -v ref 128 0 0 0 0 0 0 0 1 127 -v ref ( ) 128
max509/max510 where nb represents the digital input word. since agnd is common to all four dacs, all outputs will be offset by v bias in the same manner. do not bias agnd more than +1v above dgnd, or more than 2.5v below dgnd. figures 14 and 15 illustrate the generation of negative offsets with bipolar outputs. in these circuits, agnd is biased negatively (up to -2.5v with respect to dgnd) to provide an arbitrary negative output voltage for a 0 input code. the output voltage at outa is: outa = -(r2/r1)(2.5v) + (nb/256)(2.5v)(r2/r1+1) where nb represents the digital input word. since agnd is common to all four dacs, all outputs will be offset by v bias in the same manner. table 3, with v ref = 2.5v, shows the digital code vs. output voltage for figure 14 and 15's circuits with r1 = r2. the icl7612 op amp is chosen because its common-mode range extends to both supply rails. quad, serial 8-bit dacs with rail-to-rail outputs 16 ______________________________________________________________________________________ figure 11. max509 unipolar output circuit refd dac a dac b dac c dac d refc refb refa max509 outa outb outc outd serial interface not shown reference inputs (v ss to v dd ) 2 1 20 19 v dd +5v 16 517 418 3 -5v (or gnd) 68 v ss agnd dgnd figure 12. max510 unipolar output circuit dac a dac b dac c dac d refab max510 outa outb outc outd serial interface not shown reference inputs (v ss to v dd ) 2 1 16 15 v dd +5v 414 3 -5v (or gnd) 56 v ss agnd dgnd refcd 13 figure 13. max509/max510 agnd bias circuits (positive offset) dac a max509 5 18 agnd 2 outa dgnd v ss refa v dd 3 8 v in v bias 6 +5v -5v (or gnd) dac a max510 4 14 agnd 2 outa dgnd v ss refab v dd 3 6 v in v bias 5 +5v -5v (or gnd) serial interface not shown
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 17 figure 14. max509 agnd bias circuit (negative offset) dac a dac b dac c dac d max509 outa outb outc outd serial interface not shown reference inputs 2 1 20 19 v dd +5v 16 517 4 18 3 -5v 8 v ss agnd dgnd 6 0.1 m f 0.1 m f max873 +5v 0.1 m f r1 330k 0.1% +5v +2.5v 0.1 m f 0.1 m f -5v 6 8 7 2 3 1 r2 330k 0.1% icl7611a 4-quadrant multiplication each dac output may be configured for 4-quadrant multiplication using figure 16 and 17's circuit. one op amp and two resistors are required per channel. with r1 = r2: v out = v ref [2(nb/256)-1] where nb represents the digital word in dac register a. the recommended value for resistors r1 and r2 is 330k (?.1%). table 3 shows the digital code vs. out- put voltage for figure 16 and 17's circuit.
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs 18 ______________________________________________________________________________________ figure 15. max510 agnd bias circuit (negative offset) dac a dac b dac c dac d max510 outa outb outc outd serial interface not shown reference inputs 2 1 16 15 v dd +5v 13 4 14 3 -5v 6 v ss agnd dgnd 5 0.1 m f 0.1 m f max873 +5v 0.1 m f r1 330k 0.1% +5v +2.5v 0.1 m f 0.1 m f -5v 6 8 7 2 3 1 r2 330k 0.1% icl7611a 6 4 2 dac a dac b dac c dac d max509 outa outb outc outd serial interface not shown reference inputs (v ss to v dd ) 2 1 20 19 v dd +5v 16 517 418 3 agnd or -5v 8 v ss agnd dgnd 6 *connect icl7612a pin 8 to agnd +5v 0.1 m f 0.1 m f r1 0.1 m f r2 -5v v out +5v r1 r2 0.1 m f v out 0.1 m f -5v 0.1 m f icl7612a* icl7612a* figure 16. max509 bipolar output circuit
max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ______________________________________________________________________________________ 19 dac a dac b dac c dac d max510 outa outb outc outd serial interface not shown reference inputs 2 1 16 15 v dd +5v 13 414 3 agnd or -5v 6 v ss agnd dgnd 5 *connect icl7612a pin 8 to agnd +5v 0.1 m f 0.1 m f r1 0.1 m f r2 -5v v out +5v r1 r2 0.1 m f v out 0.1 m f -5v 0.1 m f icl7612a* icl7612a* figure 17. max510 bipolar output circuit top view 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 outc outd v dd refcd refab v ss outa outb max510 cs sclk din clr dout ldac dgnd agnd dip/wide so ____pin configurations (continued) max509 outa dac a dac b dac c dac d refa refb dac reg a decode control input reg a dac reg b input reg b dac reg c input reg c dac reg d input reg d 12-bit shift register sr control cs din sclk refc refd outb outc outd dout ldac clr v dd dgnd v ss agnd __functional diagrams (continued)
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1996 maxim integrated products printed usa is a registered trademark of maxim integrated products. max509/max510 quad, serial 8-bit dacs with rail-to-rail outputs ___________________chip topography _ordering information (continued) part temp. range pin-package max509aepp -40? to +85? 20 plastic dip max509bepp -40? to +85? 20 plastic dip max509aewp -40? to +85? 20 wide so ? ? 1/2 ? max509bewp -40? to +85? 20 wide so ? 1/2 max509aeap -40? to +85? 20 ssop ? max509beap -40? to +85? 20 ssop ? 1/2 max509amjp -55? to +125? 20 cerdip** ? max509bmjp -55? to +125? 20 cerdip** ? 1/2 max510 acpe 16 plastic dip ? max510bcpe 0? to +70? 16 plastic dip ? 1/2 max510acwe 0? to +70? 16 wide so ? max510bcwe 0? to +70? 16 wide so ? 1/2 max510aepe -40? to +85? 16 plastic dip ? max510bepe -40? to +85? 16 plastic dip ? 1/2 max510aewe -40? to +85? 16 wide so ? max510bewe -40? to +85? 16 wide so ? 1/2 0? to +70? max510amje -55? to +125? 16 cerdip** ? max510bmje -55? to +125? 16 cerdip** ? 1/2 **contact factory for availability and processing to mil-std-883. ________________________________________________________package information l dim a a1 b c d e e h l a min 0.068 0.002 0.010 0.005 0.278 0.205 0.301 0.022 0? max 0.078 0.008 0.015 0.009 0.289 0.212 0.311 0.037 8? min 1.73 0.05 0.25 0.13 7.07 5.20 7.65 0.55 0? max 1.99 0.21 0.38 0.22 7.33 5.38 7.90 0.95 8? inches millimeters a 20-pin plastic shrink small-outline package h e d a a1 c 0.127mm 0.004in. b 0.65 bsc 0.0256 bsc 21-0003a e refc (refcd) sclk cs refb (refab) agnd v ss outc outd v dd clr dout ldac 0.121" (3.07mm) 0.128" (3.25mm) dgnd refa (refab) din refd (refcd) outa outb max509/max510 note: labels in ( ) are for max510 only. transistor count: 2235; substrate connected to v dd . tue (lsb)

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